This invention relates to a storage element for an integrated circuit device and a method for setting desired signal levels at such storage element. More particularly, this invention relates to a modified storage element having an additional read/write input which may be controlled to allow test circuitry to define a desired signal level for the storage element.
During testing of integrated circuits (ICs), it is necessary to force specific logic states at select storage elements. Typically, this has been accomplished by using the primary input pins of the IC. As integrated circuits become more complex, it is more difficult to define the desired logic states using the primary input pins of the IC. For example, in complex ICs, the states of many logic gates and storage element output lines may not be defined readily through the primary pins because of the many circuit levels between such gates or elements and the primary input pins.
One approach for defining logic states at a storage element is commonly referred to as SCAN. See "Design For testability--A Survey" by T. W. Williams and K. P. Parker, Proceedings IEEE, Vol. 71, pp98-112, January 1983; and "A Logic Design Structure For LSI Testing" by E. B. Eichelberger and T. W. Williams, Proceedings 14th Design Automation Conference, June 1977 77CH1216-1C, pp. 462-468. Also see "Built-in Self-Test Techniques" and "Built-in Self-Test Structures" by E. J. McClusky, IEEE Design and Test, Vol. 2, No. 2, pp. 437-452. Also see U.S. Pat. Nos. 3,806,891 (Eichelberger et. al.); 3,761,675; 4,293,919 (Dasgupta et. al.) and 4,513,418 (Bardell, Jr. et. al.) assigned to the IBM Corporation which disclose the serial connection of flip-flops into a shift register to allow access to them through "fewer" test points.
According to the SCAN approach, the integrated circuit is designed to tie the select storage elements to one or more shift register chains. The shift registers can thereafter be loaded through test contacts or through the primary input pins during a test, enabling the desired logic states to be loaded to the select storage elements. In effect, the conventional SCAN approaches multiplex the input to the storage element so that during testing, the test circuitry generates the input signal, whereas during normal operation the normal integrated circuit logic generates the input signal.
Drawbacks of the SCAN approach are the resulting increase in surface area, the resulting increase in circuit delay times during normal operation and cumbersome design constraints. Typically an integrated circuit designed to conform to the SCAN approach suffers a 10% speed loss and 20% area loss attributable to the SCAN methodology. Accordingly, a more effective approach for setting predefined levels at select storage elements during testing is needed.
Other approaches for defining logic states or monitoring internal components of circuitry, including integrated circuits, are described in U.S. Pat. No. 4,613,970 for INTEGRATED CIRCUIT DEVICE AND METHOD OF DIAGNOSING THE SAME; EPO patent publication number 223 714 A2 for SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH TEST CIRCUIT; U.S. Pat. No. 4,517,672 for METHOD AND ARRANGEMENT FOR AN OPERATIONAL CHECK OF A PROGRAMMABLE LOGIC ARRAY; IBM Technical Disclosure Bulletin Vol. 8, no. 5 October 1965, "Voltage Checking Device" by G. Canard and A. Potocki; and U.S. Pat. No. 3,795,859 for METHOD AND APPARATUS FOR DETERMINING THE ELECTRICAL CHARACTERISTICS OF A MEMORY CELL HAVING FIELD EFFECT TRANSISTORS.
In commonly-assigned U.S. Pat. No. 4,749,947 of the same inventor issued Jun. 7, 1988 for GRID-BASED, "CROSS-CHECK" TEST STRUCTURE FOR TESTING INTEGRATED CIRCUITS, a functionally independent, internal grid-based structure for an integrated circuit is disclosed enabling testing of complex integrated circuits. Referring to such structure as shown in FIG. 1 herein, a grid-structure 10 on an integrated circuit 11 is formed of individually accessible probe lines 12 and sense/control lines 14 with electronic switches 16 at the crossings. A probe line 12 is coupled to a switch 16 for defining the switch "ON" or "OFF" state. One end of the switch 16 is coupled to a test point 18 of the integrated circuit 11, while the other end is coupled to a sense/control line 14 for monitoring a signal from the test point 18. Activating a select switch 16 through a corresponding probe line 12 enables monitoring or exciting a test point. The integrated circuit includes primary input pins 19, probe line contacts 20 and sense line contacts 21. The test points 18 are coupled to the input line or output line of a corresponding gate G.
The grid structure described above is used for observing signals at the test points 18. The switches 16 coupled to the test points 18 have a high impedance so as to provide less current drive than the logic gates G. As a result, the switch lines do not alter or disturb the internal signals of the integrated circuit 11 during observation.
While testing an integrated circuit, it is typical to apply test signals to the primary input pins of the IC to form a test pattern which defines specific data input signals to select internal elements of the IC (e.g., SCAN techniques). In addition, it is also known to define such data input signals through test points coupled directly (e.g., "Cross-Check" matrix) or indirectly (e.g., SCAN techniques) to the select internal elements. A method of setting desired signal levels for storage elements of an IC by forcing logic states on the select storage elements is needed. Setting the desired signal levels by forcing (e.g., overpowering) logic states otherwise occurring at the select storage elements is needed.
The commonly-assigned co-pending U.S. patent application Ser. No. 554,313, filed Jul. 17 1990, included herein by reference, describes an apparatus and method for setting desired signal levels at select storage elements. According to such application, the desired signal level may be forced at the output, input or an internal point of the storage element. According to the present invention herein, a related method and apparatus for setting a desired signal level at an internal point of a modified storage element is described.